To cope with recent electronic devices that are reduced in size and have high density, there is a demand for high-performance and high-density semiconductor components. Thus, semiconductor devices (semiconductor packages) are being reduced in size and weight at a high pace. In such a trend, there are leadless semiconductor devices (leadless packages), which have no leads extending to the outside, such as, a quad flat non-leaded package (QFN package) and a small outline non-leaded package (SON package) (e.g., refer to Japanese Laid-Open Patent Publication Nos. 2003-309241 and 2003-309242).
FIG. 22 is a cross-sectional view illustrating one example of a leadless semiconductor device 90.
In the semiconductor device 90, a semiconductor element 92 is mounted on a die pad 91, and the semiconductor element 92 and leads 93 are electrically connected by metal wires 94. Each lead 93 includes an upper surface electrically connected to the semiconductor element 92 and a lower surface (reverse surface) connected to a motherboard or the like. In the lead 93, the upper surface is wider than the lower surface. More specifically, the lead 93 has the form of a step. In other words, each lead 93 includes a thin distal portion 93A. In the semiconductor device 90, an encapsulation resin 95 encapsulates the semiconductor element 92, the metal wires 94, and the distal portions 93A of the leads 93. The encapsulation resin 95 extends into the lower side of the distal portion 93A of each lead 93 so that the gap between the lead 93 and the die pad 91 is filled with the encapsulation resin 95. This produces an anchor effect that limits dropout of the leads 93 from the encapsulation resin 95. In this manner, the thin distal portions 93A of the leads 93 caught in the encapsulation resin 95 each have the form of an anchor and limit the dropout of the leads 93.
In the semiconductor device 90, the reverse surface of each lead 93, which is exposed from the encapsulation resin 95, functions as an external connection terminal.